Linear to physical address translation with support for page attributes

摘要

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a plurality of registers; at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address; a page miss handler to perform a table walk; and a physical address return register, wherein the physical address return register is a 64-bit register, wherein the processor is to receive an instruction to translate a virtual address to a first physical address, wherein the instruction is a kernel level privileged instruction, and wherein the instruction is to cause the processor, when in a 64-bit mode, to:
translate the virtual address to the first physical address;store the first physical address translated from the virtual address in the physical address return register; andstore at least one attribute associated with the first physical address translated from the virtual address in the physical address return register.