| 发明名称 | Serial memory with fast read with look-ahead | ||
| 摘要 | A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire address has been received through the serial interface. The controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out. | ||
| 申请公布号 | US9159442(B2) | 申请公布日期 | 2015.10.13 |
| 申请号 | US201213666723 | 申请日期 | 2012.11.01 |
| 申请人 | MICROCHIP TECHNOLOGY INCORPORATED | 发明人 | Czeides Silvia |
| 分类号 | G11C7/00;G11C16/32;G11C5/06;G11C7/22 | 主分类号 | G11C7/00 |
| 代理机构 | Slayden Grubert Beard PLLC | 代理人 | Slayden Grubert Beard PLLC |
| 主权项 | 1. A serial memory comprising: memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory blocks which are accessed in parallel before an entire address has been received through said serial interface, wherein the controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out, wherein most significant data bits of each memory block are accessible separately via a plurality of separate data lines and wherein remaining data bits of each memory block are coupled in parallel via common data lines. | ||
| 地址 | Chandler AZ US | ||