发明名称 Method and apparatus for connecting memory dies to form a memory system
摘要 A method, system and apparatus for connecting multiple memory device dies 51-54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52-54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop.
申请公布号 US9159647(B2) 申请公布日期 2015.10.13
申请号 US201313750046 申请日期 2013.01.25
申请人 NovaChips Canada Inc. 发明人 Choi Byoung Jin
分类号 G11C5/06;H01L23/48;H01L21/50;G11C5/04;H05K1/02;H01L25/065;H05K1/18 主分类号 G11C5/06
代理机构 Borden Ladner Gervais LLP 代理人 Hung Shin;Borden Ladner Gervais LLP
主权项 1. A memory system comprising: a substrate having a first side and a second side; first memory devices mounted to the first side of said substrate, and; second memory devices mounted to the second side of said substrate in staggered formation relative to said first memory devices; and, vias extending from the first side to the second side of the substrate and connected to connections of the first memory devices and the second memory devices.
地址 Ottawa, Ontario CA