Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers

摘要

Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

主权项

1. An electronic apparatus, comprising:
a first level package structure comprising a silicon space transformer chip carrier structure and an integrated circuit chip flip chip mounted on a first surface of the silicon space transformer chip carrier structure using a first pattern of electrical contacts with pitch P1; and a second level package substrate comprising a second pattern of electrical contacts with pitch P2, wherein P2>P1, formed on a mounting surface thereof, wherein the first level package structure is mounted to the mounting surface of the second level package substrate with the silicon space transformer chip carrier structure providing space transforming electrical interconnections between the first pattern of electrical contacts and the second pattern of electrical contacts on the mounting surface of the second level package structure, and wherein the silicon space transformer chip carrier structure comprises:
a planar silicon substrate having a first planar surface and a second planar surface opposing the first planar surface;a plurality of annular conductive through-vias formed in the planar silicon substrate to surround an inner core of silicon substrate material and to provide vertical electrical connections extending through the planar silicon substrate between the first planar surface and the second planar surface.