发明名称 Semiconductor device having hierarchical bit line structure
摘要 A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.
申请公布号 US9159401(B2) 申请公布日期 2015.10.13
申请号 US201514597471 申请日期 2015.01.15
申请人 PS4 Luxco S.a.r.l. 发明人 Nagata Kyoichi
分类号 G11C5/02;G11C5/06;G11C11/24;G11C7/00;G11C7/02;G11C11/4091;G11C7/12;G11C7/08;G11C11/4097 主分类号 G11C5/02
代理机构 代理人
主权项 1. A method for operating a dynamic random access memory having a sense amplifier connected to first and second global bit lines, each global bit line connected to a plurality of local bit lines through a hierarchical switch, each local bit line connected to a plurality of memory cell capacitors through a selection transistor, the method comprising: precharging the sense amplifier while a first hierarchical switch connecting the first global bit line to a first local bit line and a second hierarchical switch connecting the second global bit line to a second local bit line are in an ON-state; turning off the first hierarchical switch and turning on a third hierarchical switch connecting the first global bit line to third local bit line; driving a first word line connected to a first selection transistor to a first level to connect a first memory cell capacitor to the third local bit line; activating the sense amplifier; driving the first word line to a second level to disconnect the first memory cell capacitor from the third local bit line; and precharging the sense amplifier while the third hierarchical switch and the second hierarchical switch are in an ON-state.
地址 Luxembourg LU