CUT MASK DESIGN LAYERS TO PROVIDE COMPACT CELL HEIGHT

摘要

Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

主权项

1. A method of designing an integrated circuit (IC) layout, comprising:
providing a plurality of gate_zero (G0) lines within a graphical representation of the layout; providing a plurality of metal_zero (M0) lines within a graphical representation of the layout, wherein a G0 line is interspersed between neighboring M0 lines to define a transistor structure; providing a gate_zero-to-metal_zero (G0-M0) connection to couple the G0 line to a M0 line, wherein the G0-M0 connection perpendicularly overlaps the G0 lines and the M0 lines; and generating both a G0 cut mask design layer and an M0 cut mask design layer that each overlap the G0-M0 connection, wherein the G0 cut mask design layer is used to cut the G0 line so an end of the cut G0 line is spaced a first predetermined distance from a nearest edge of the G0-M0 connection, and wherein the M0 cut mask design layer is used to cut the M0 line so an end of the cut M0 line is spaced a second predetermined distance from the nearest edge of the G0-M0 connection.