LAYOUT CHECKING SYSTEM FOR MULTIPLE-PATTERNING GROUP ASSIGNMENT CONSTRAINTS

摘要

A method includes a step of extracting multiple-patterning group assignment information of one or more layout patterns from a layout design. The layout design corresponds to a circuit design, and the layout patterns correspond to a node of the circuit design. Whether the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node is determined by a hardware processor.