| 发明名称 |
VOLTAGE REGULATION CIRCUIT |
| 摘要 |
A circuit may include a low-dropout (LDO) voltage regulator. The LDO voltage regulator may include an output coupled to a supply of a load circuit. The LDO voltage regulator may be configured to provide a supply voltage to the load circuit. The circuit may also include a current source coupled to the supply of the load circuit and the output of the LDO voltage regulator. The current source may be configured to supply current to the load circuit in a manner that reduces current supplied to the load circuit by the LDO voltage regulator. |
| 申请公布号 |
US2015286232(A1) |
申请公布日期 |
2015.10.08 |
| 申请号 |
US201414248175 |
申请日期 |
2014.04.08 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
PARIKH Samir |
| 分类号 |
G05F1/56;G06F17/50 |
主分类号 |
G05F1/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit comprising:
a low-dropout (LDO) voltage regulator including an output coupled to a supply of a load circuit, the LDO voltage regulator being configured to provide a supply voltage to the load circuit; and a current source coupled to the supply of the load circuit and the output of the LDO voltage regulator, the current source being configured to supply current to the load circuit in a manner that reduces current supplied to the load circuit by the LDO voltage regulator. |
| 地址 |
Kawasaki-shi JP |
