| 摘要 |
Disclosed is a clock duty ratio adjustment circuit, comprising: a clock time delay processing module and a clock adjustment module, wherein the clock time delay processing module is configured to conduct time delay on an input clock signal of the clock duty ratio adjustment circuit to obtain a time delay clock signal, and acquire an output clock signal of the clock duty ratio adjustment circuit to adjust the time delay between the input clock signal and the time delay clock signal according to the duty ratio of the output clock signal; and the clock adjustment module is configured to adjust the duty ratio of the input clock signal according to the time delay clock signal to obtain the output clock signal. Also disclosed is a multi-phase clock generator. |
