SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD GAP FILL

摘要

An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

主权项

1. A method of forming an integrated circuit, comprising the steps of:
providing a semiconductor substrate; forming a plurality of PMOS gate structures disposed proximate to each other; forming a plurality of NMOS gate structures disposed proximate to each other; forming source/drain spacers on lateral surfaces of gate offset spacers of said PMOS gate structures; forming source/drain spacers on lateral surfaces of gate offset spacers of said NMOS gate structures; removing said source/drain spacers from said PMOS gate structures and said source/drain spacers from said NMOS gate structures; forming a CESL spacer layer over an existing top surface of said integrated circuit, including over said PMOS gate structures and said NMOS gate structures; performing an anisotropic reactive ion etch (RIE) process which removes said CESL spacer layer from top surfaces of said PMOS gate structures and said NMOS gate structures and from portions of said existing top surface of said integrated circuit between said PMOS gate structures and said NMOS gate structures, leaving said CESL spacer layer on lateral surfaces of said PMOS gate structures and said NMOS gate structures so as to form sloped CESL spacers which have a height of ¼ to ¾ of a height of said PMOS gate structures and said NMOS gate structures; forming a CESL over said PMOS gate structures and said sloped CESL spacers on said lateral surfaces of said gate offset spacers of said PMOS gate structures, said CESL comprising silicon nitride, said CESL being free of reentrant surface profiles between said PMOS gate structures; and forming a PMD layer over said CESL.