SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS

摘要

Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.

主权项

1. A neural core circuit comprising:
a pseudo-random number generator (PRNG) for generating random numbers; a plurality of incoming electronic axons; a plurality of neural modules, wherein each neural module maintains one or more configurable probability values, wherein each neural module integrates incoming spikes probabilistically based in part on at least one random number generated by the PRNG and at least one of said probability values, wherein each neural module generates outgoing spikes probabilistically based in part on a comparison between at least one random number generated by the PRNG and at least one of said probability values, and wherein each neural module represents a noisy-OR gate; and a plurality of electronic synapses interconnecting the axons with the neural modules, wherein each synapse interconnects an axon with a neural module, and wherein each neural module receives incoming spikes from interconnected axons.