MULTI-GRANULAR CACHE COHERENCE

摘要

Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.

主权项

1. A die in a multi-core processor architecture, the die comprising:
a first tile including a first cache and a first processor core, wherein the first tile is configured to store a particular block and a region of blocks, wherein the region of blocks includes two or more blocks; a second tile configured in communication with the first tile, wherein the second tile includes a second cache and a second processor core; a directory controller configured in communication with the first tile and the second tile, wherein the directory controller is effective to control a directory for the die; wherein the directory controller is configured to:
determine a block level coherence state associated with the particular block;determine a region level coherence state associated with the region of blocks, wherein the region level coherence state is based on a respective block level coherence state of each respective block among the two or more blocks of the region of blocks;communicate to the first tile the block level coherence state of the particular block and the region level coherence state of the region of blocks; andwherein the first tile is configured to:receive the block level coherence state and the region level coherence state from the directory controller;identify the block level coherence state of the particular block and the region level coherence state of the region of blocks; andstore the block level coherence state associated with the particular block in the first cache and the region level coherence state in association with the region of blocks in the first cache.