MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

摘要

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

主权项

1. A controller to control operations of a memory component, the controller comprising;
a first circuit to transmit commands to the memory component, the commands including a read command that specifies data to be accessed from a memory core of the memory component; a second circuit to receive data sent by the memory component via an external bus, the data sent by the memory component in response to the read command; calibration circuitry, operable during calibration, to receive at least a first data pattern and a second data pattern from the memory component, the first data pattern and the second data pattern being provided from pattern register circuitry in the memory component, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the memory component onto the external bus in response to one of the commands.