DIELECTRIC LINER ADDED AFTER CONTACT ETCH BEFORE SILICIDE FORMATION

摘要

A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

主权项

1. An integrated circuit (IC), comprising:
a substrate having a semiconductor surface,
a plurality of Metal-Oxide Semiconductor (MOS) transistors formed in said semiconductor surface including an NMOS transistor and a PMOS transistor each including a source, and a drain at least partially in said semiconductor surface, and a gate electrode on a gate dielectric on said semiconductor surface, dielectric spacers on sidewalls of said gate electrode, and a pre-metal dielectric (PMD) layer over said gate electrode and over said source and said drain;contact holes through said PMD layer to provide contacts to said gate electrode, said source and said drain for said NMOS and said PMOS transistor;a dielectric liner on sidewalls of said contact holes, anda metal silicide layer on at least said contacts to said source and said drain for said NMOS transistor and said PMOS transistor.