发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
摘要 In a step F2, an isolation region and an element formation region are formed in an SOI substrate. In a step F3, an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F4, a gate electrode is formed. In a step F5, extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F6, an elevated epitaxial layer is formed in the SOI region.
申请公布号 US2015287746(A1) 申请公布日期 2015.10.08
申请号 US201514674838 申请日期 2015.03.31
申请人 RENESAS ELECTRONICS CORPORATION 发明人 SHINKAWATA Hiroki;IWAMATSU Toshiaki
分类号 H01L27/12;H01L21/8234;H01L29/06;H01L21/762;H01L21/027;H01L29/167;H01L21/84;H01L29/66 主分类号 H01L27/12
代理机构 代理人
主权项 1. A method of manufacturing a semiconductor device, comprising processes of: preparing a substrate portion having a semiconductor layer formed on a surface of a semiconductor substrate with an insulating layer being interposed; forming an isolation region in said substrate portion; defining a first region and a second region adjacent to each other with respect to said substrate portion, and forming a first element formation region and a first dummy element formation region in said first region and forming a second element formation region and a second dummy element formation region in said second region by exposing said semiconductor substrate and said isolation region by allowing said semiconductor layer and said insulating layer located in said first region to remain and removing said semiconductor layer and said insulating layer located in said second region; forming a first gate electrode and a first dummy gate electrode in said first region and forming a second gate electrode and a second dummy gate electrode in said second region; forming a cover portion covering said first element formation region and said first dummy element formation region; introducing an impurity of one conductivity type into said second element formation region in said second region with at least said cover portion serving as a mask after said cover portion is formed; and forming an elevated epitaxial layer in said first element formation region with an epitaxial growth method, in said process of forming an isolation region, said isolation region being formed such that said isolation region is exposed along an entire step formed at a boundary between said first region and said second region by removing said semiconductor layer and said insulating layer located in said second region.
地址 Kawasaki-shi JP