SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

摘要

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

主权项

1. Controller circuitry comprising:
A. state machine circuitry having a command 0 input, a command 1 input, a frame marker input, a scan clock input, a test enable input, a clock 2 enable output, a parallel scan enable output, and a serial scan enable output; B. first gate circuitry having a first input connected to clock 2 enable output, a second input connected to the scan clock input, and a clock 2 output; and C. second gate circuitry having a first input connected to the scan clock input, a second input connected to the test enable input, and a clock 1 output.