发明名称 キャッシュフラッシュ制御装置
摘要 <p><P>PROBLEM TO BE SOLVED: To solve the problems that, in the technique of flushing all at once, store instructions accessing an area inside the same block of a cache, the effect is reduced when the distance of vector store instructions becomes long and there is no effect when the distance becomes a block size or longer. <P>SOLUTION: The cache flush control device includes a cache address generation part and a cache address control part. On a cache in an information processor which performs vector operation processing, two or more pieces of data are stored. When the information processor executes the vector store instruction, the cache address generation part generates a group of addresses which are the addresses of the areas to be accessed by the vector store instruction and include the same tag. The cache address control part executes flush processing of invalidating all at once, the data group of the areas which correspond to the address group respectively and are continuous over a plurality of blocks among the two or more pieces of the data. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP5791091(B2) 申请公布日期 2015.10.07
申请号 JP20090252272 申请日期 2009.11.02
申请人 发明人
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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