| 摘要 |
The present document relates to a clock enabling circuit (100) for providing a gated clock signal (CLK_G) in response to receiving clock request information (REQ), the clock enabling circuit (100) comprising:
- a clock request input (110) for receiving the clock request information (REQ);
- a clock input (120) for receiving a clock signal;
- a flip-flop stage (130) comprising at least a first and a second flip-flop (131, 132), wherein an output of the first flip-flop (131) is coupled with the input of a second flip-flop (132);
- a first sub-circuitry (140) comprising at least a first input being coupled with the clock request input (110) and an output being coupled with the flip-flop stage (130) for providing a set information (SET) to the flip-flop stage (130) in response to the receipt of the clock request information (REQ), the flip-flop stage (130) being configured to provide a clock enabling information (CLK_EN) in response to receiving the set information (SET);
- a second sub-circuitry (150) comprising a first and a second input, the first input being coupled with the clock input (120) and the second input being coupled with the flip-flop stage (130), the second sub-circuitry (150) comprising an output for providing the gated clock signal (CLK_G) in response to receiving the clock enabling information (CLK_EN);
wherein the clock inputs of the first and second flip-flop (131, 132) are coupled with the output of the second sub-circuitry (150) in order to be triggered by the gated clock signal (CLK_G). |
