发明名称 |
Delay-compensated error indication signal |
摘要 |
A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices. |
申请公布号 |
GB2524852(A) |
申请公布日期 |
2015.10.07 |
申请号 |
GB20140017065 |
申请日期 |
2012.03.31 |
申请人 |
INTEL CORPORATION |
发明人 |
KULJIT BAINS;GEORGE VERGIS |
分类号 |
G11C29/42;G11C5/04;G11C7/10;G11C29/44 |
主分类号 |
G11C29/42 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|