Memory interface with reduced read-write turnaround delay

摘要

Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links.

主权项

1. A memory controller for use with a memory integrated circuit (IC) having a plurality of bidirectional signal interfaces and a plurality of memory banks, the memory controller comprising:
a plurality of signal interfaces to communicate signals via a plurality of communication links with respective ones of the bidirectional signal interfaces of the memory IC; a command interface to convey settings of a routing circuit in the memory IC such that the memory IC may properly route the signals between the plurality of communication links and the plurality of memory banks; queues to store a set of commands for transmission to the memory IC; control logic to determine the settings of a routing circuit in the memory controller configured to route read data and write data, corresponding to the set of commands, between the queues and the plurality of signal interfaces, and to determine the settings of the routing circuit in the memory IC, each of the memory controller routing circuit settings and memory IC routing circuit settings based at least in part on the set of commands in the queues; and wherein the memory IC routing circuit settings are to cause the routing circuit in the memory IC to use a first link of the plurality of communications links in a unidirectional manner, to receive write data irrespective of which of the plurality of banks is the subject of a write command, and to use a second link of the plurality of communication links in a unidirectional manner, to transmit read data irrespective of which of the plurality of banks is the subject of a read command, so as to avoid a driver turnaround time associated with the bidirectional signal interfaces.