Fault tolerant design for large area nitride semiconductor devices

摘要

A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

主权项

1. A nitride semiconductor device comprising:
a substrate; a nitride semiconductor layer formed on a device area of the substrate, the nitride semiconductor layer defining a plurality of active regions for an array of islands of a multi-island transistor, the array of islands extending in first and second directions over the device area; each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area; each island having a source electrode, a drain electrode and a gate electrode formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, the gate electrode being formed on the nitride semiconductor layer over the channel region and running between the source and drain peninsulas across the island; each source electrode having a source contact area, each drain electrode having a drain contact area, each gate electrode having a gate contact area; the source, drain and gate electrodes of each island of the array of islands being arranged so that each island is electrically isolated from the source, drain and gate electrodes of neighboring islands in at least one of said first and second directions; an overlying interconnect structure comprising at least one dielectric isolation layer and at least one metallization layer; the at least one dielectric isolation layer being patterned to provide contact openings only to source, drain and gate contact areas of non-defective islands, while electrically isolating contact areas of defective islands; and the at least one metallization layer providing: a source interconnection interconnecting in parallel the source electrodes of multiple islands; a drain interconnection interconnecting in parallel the drain electrodes of multiple islands; and a gate interconnection interconnecting the gate electrodes of multiple islands to form a common gate, said overlying interconnect structure thereby selectively interconnecting non-defective islands of the multi-island transistor and providing electrical isolation of defective islands.