发明名称 Network based data traffic detection and control
摘要 A network-based apparatus for imposing a minimum transmit latency on data packets of a prescribed data type on a network includes at least one processor. The processor is operative: (i) to receive a data packet of the prescribed data type; (ii) to determine an elapsed time since an arrival of the received data packet at the apparatus; (iii) when the elapsed time is equal to or greater than the minimum transmit latency, to transmit the data packet; and (iv) when the elapsed time is less than the minimum transmit latency, to wait an amount of time at least equal to a difference between the elapsed time and the minimum transmit latency and then to transmit the data packet. The apparatus further includes memory coupled to the processor, the memory being configurable for storing data utilized by the processor.
申请公布号 US9154421(B2) 申请公布日期 2015.10.06
申请号 US200611443393 申请日期 2006.05.30
申请人 Intel Corporation 发明人 Sonnier David P.
分类号 H04L12/54;H04L12/801;H04L12/813;H04L12/815;H04L12/853;H04L12/851;H04L12/841;H04L12/24;H04L12/26 主分类号 H04L12/54
代理机构 Schwabe, Williamson & Wyatt, P.C. 代理人 Schwabe, Williamson & Wyatt, P.C.
主权项 1. A network-based apparatus for imposing at least a prescribed minimum transit latency on data packets of a prescribed data type on a network, the apparatus comprising: at least one processor operative: (i) to receive a data packet of the prescribed data type; (ii) to determine an elapsed time since an arrival of the received data packet at the apparatus; (iii) when the elapsed time is equal to or greater than the prescribed minimum transit latency, to transmit the data packet; and (iv) when the elapsed time is less than the prescribed minimum transit latency, to wait an amount of time at least equal to a difference between the elapsed time and the prescribed minimum transit latency and then to transmit the data packet, thereby ensuring that the data packet is transmitted with a latency greater than or equal to the prescribed minimum transmit latency; memory coupled to the at least one processor, the memory being configurable for storing data utilized by the at least one processor; and circuitry operative to receive a packet stream and to detect whether the packet stream comprises the data packets of the prescribed data type based on a traffic pattern analysis of the packet stream; wherein the minimum transit latency is imposed only on a specified percentage of the data packets of the prescribed data type, said specified percentage of the data packets of the prescribed data type being less than all of the data packets of the prescribed data type.
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