发明名称 Techniques for forming non-planar germanium quantum well devices
摘要 Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
申请公布号 US9153671(B2) 申请公布日期 2015.10.06
申请号 US201314141648 申请日期 2013.12.27
申请人 INTEL CORPORATION 发明人 Pillarisetty Ravi;Kavalieros Jack T.;Rachmady Willy;Shah Uday;Chu-Kung Benjamin;Radosavljevic Marko;Mukherjee Niloy;Dewey Gilbert;Jin Been Y.;Chau Robert S.
分类号 H01L29/66;B82Y10/00;H01L29/267;H01L29/775;H01L29/778;H01L21/76;H01L29/78;H01L29/10;H01L29/51 主分类号 H01L29/66
代理机构 Finch & Maloney PLLC 代理人 Finch & Maloney PLLC
主权项 1. A non-planar semiconductor device, comprising: a silicon substrate; a silicon germanium barrier layer formed over the silicon substrate; a germanium layer formed over the silicon germanium barrier layer, wherein at least a portion of the germanium layer comprises a germanium fin structure having a top surface and laterally opposite sidewall surfaces; a silicon capping layer formed on at least a portion of the germanium fin structure, wherein the silicon capping layer covers the top surface and sidewall surfaces of the germanium fin structure; a gate dielectric layer formed on the silicon capping layer, the gate dielectric layer formed atop the portion of the silicon capping layer that covers the top surface of the germanium fin structure and formed adjacent to portions of the silicon capping layer that cover the sidewall surfaces of the germanium fin structure; and a gate electrode layer formed on the gate dielectric layer.
地址 Santa Clara CA US