Gate rounding for reduced transistor leakage current

摘要

Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.

主权项

1. A transistor comprising:
a substrate region including a source region and a drain region; and a gate region including,
a main gate portion formed over a portion of the substrate region between the source region and the drain region; anda first gate tip formed at a first end of the main gate portion that extends beyond, without overlapping, the portion of the substrate region between the source region and the drain region, the first gate tip joined with the first end at a junction and extending transversely from the first end, and wherein a rounded gate portion is formed at the junction between the first gate tip and the main gate portion.