Measurement circuit and test apparatus

摘要

Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level.

主权项

1. A measurement circuit that measures a signal under measurement input thereto, comprising:
a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on an expected value pattern of the signal under measurement and the threshold level, the timing adjusting section including:
a variable delay circuit that delays at least one of the comparison timing input to the logic comparing section and the signal output by the level comparing section, according to a logic value of the expected value pattern and the threshold level,a characteristic information storage section that is supplied with characteristic information indicating, for each logic value of the signal under measurement, a delay amount of the signal output by the level comparing section caused by a difference between the threshold level and the signal level of the signal under measurement input to the level comparing section, anda delay setting section that sets a delay amount in the variable delay circuit based on the delay amount corresponding to the logic value of the expected value pattern in the characteristic information.