发明名称 Network relay apparatus and control method thereof
摘要 A network relay apparatus includes: a clock generation circuit, a processing circuit, a load detector and a clock cutoff circuit. The clock generation circuit is configured to generate a clock signal having periodical clock pulses. The processing circuit is configured to operate in synchronism with the clock pulses, in order to process data that is to be relayed by the network relay apparatus. The load detector is configured to detect a load of processing by the processing circuit. The clock cutoff circuit is configured to cut off supply of the clock pulses from the clock generation circuit to the processing circuit in order to partially eliminate the clock pulses at a rate corresponding to the load detected by the load detector and to provide the clock signal having the partially eliminated clock pulses to the processing circuit.
申请公布号 US9154313(B2) 申请公布日期 2015.10.06
申请号 US201213720523 申请日期 2012.12.19
申请人 Alaxala Networks Corporation 发明人 Kono Tomohiko
分类号 H04L12/28;H04L12/12;H04L12/66;H04J3/06 主分类号 H04L12/28
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP
主权项 1. A network relay apparatus, comprising: a clock generation circuit configured to generate a clock signal having periodical clock pulses; a processing circuit configured to operate in synchronism with the clock pulses to process data that is to be relayed by the network relay apparatus; a load detector configured to detect a load of processing by the processing circuit; and a clock cutoff circuit, which is different from the clock generation circuit, configured to cut off supply of a plurality of clock pulses in a cycle of the periodical clock pulses from the clock generation circuit to the processing circuit, to partially eliminate, from the plurality of clock pulses in the cycle, at least one clock pulse at a rate corresponding to the load detected by the load detector, and to provide the clock signal having the partially eliminated clock pulses to the processing circuit.
地址 Kawasaki-shi JP