Multi-phase models for timing closure of integrated circuit designs

摘要

In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

主权项

1. A method of designing an integrated circuit, the method comprising:
partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes an initial top level netlist and each partition includes a partition netlist of a plurality of circuit components and a plurality of circuit pins, and wherein not all of the partitions have identical circuit components; independently designing each partition to include a plurality of circuit components and a plurality of circuit pins in response to a respective timing budget; and modeling each partition with a timing graph model to analyze timing of the top level of the circuit design including
analyzing each circuit pin of each partition for a phase attribute having a sub-property set including at least one of a plurality of timing exceptions, andgenerating a plurality of timing arcs coupled to one or more partition timing pins to form the timing graph model to model input timing and output timing for each partition in response to the respective timing budget; wherein the partitioning, the independently designing, and the modeling are implemented by a processor executing instructions.