| 主权项 |
1. A cache memory for a data processing system including a lower level memory, the cache memory comprising:
a single integrated circuit chip, including: a set-associative cache array including a plurality of congruence classes each associated with a respective one of a plurality of different possible values of an index portion of real memory addresses employed by the lower level memory, wherein the plurality of congruence classes each include a plurality of entries for caching cache lines of data retrieved from the lower level memory, wherein the plurality of entries within each of the plurality of congruence classes are distributed between a first region implemented in a first random access memory technology and a second region implemented in a second random access memory technology, wherein the first and second regions have differing performance characteristics as a consequence of differing memory technologies, and wherein the first random access memory technology has lower power consumption for read accesses than the second random access memory technology and the second random access memory technology has lower power consumption for store accesses than the first random access memory technology; a common cache directory of contents of the set-associative cache array, the common cache directory including tags of the cache lines of data in the first region and tags of the cache lines of data in the second region, wherein the common cache directory includes multiple directory entries each storing information associated with a respective cache line in the cache array a data characteristic field that indicates data characteristics of the associated cache line of data, wherein the data characteristic field comprises a saturating counter; and a cache controller that controls operation of the cache memory, wherein the cache controller, responsive to a memory access request specifying a target cache line which does not reside in the cache array, implements an allocation policy that selects the first region for initially caching the target cache line in response to the memory access request being a load request and that selects the second region for caching the target cache line in response to the memory access request being a store request, and responsive to the memory access request specifying a target cache line which does reside in the cache array, increments the saturating counter of the target cache line when either the memory access request is a load request and the target cache line resides in the first region or the memory access request is a store request and the target cache line resides in the second region, and decrements the saturating counter of the target cache line otherwise. |
