发明名称 Dynamic load and priority based clock scaling for non-volatile storage devices
摘要 This disclosure discusses systems, methods, and apparatus for dynamically scaling a clock frequency of an I/O interface to a non-volatile storage device. The scaling can be based on monitoring an idle time on the I/O interface, a priority of one or more applications having read/write requests queued for dispatch to the I/O interface, a load of the queued read/write requests on the I/O interface or a combination of priority and load. Such variables can be compared to thresholds in a frequency governor.
申请公布号 US9152214(B2) 申请公布日期 2015.10.06
申请号 US201313895640 申请日期 2013.05.16
申请人 Qualcomm Innovation Center, Inc. 发明人 Thumma Sujit Reddy
分类号 G06F1/32;G06F3/06 主分类号 G06F1/32
代理机构 Neugeboren O'Dowd PC 代理人 Neugeboren O'Dowd PC
主权项 1. A non-volatile storage system for scaling an I/O interface frequency between a I/O interface controller device and a non-volatile storage device, the system comprising: a non-volatile storage device; a processor having one or more applications running thereon, each of the one or more applications configured to make read and write requests to the non-volatile storage device; an I/O interface to the non-volatile storage device; a clock control block for the I/O interface generating a clock signal; an I/O interface controller device that sends read/write requests to the non-volatile storage device over the I/O interface at a clock frequency corresponding to the clock signal; an I/O scheduler that: runs on the processor;schedules the read and write requests to an I/O queue of a storage driver, the storage driver configured to dispatch read/write requests from the I/O scheduler to the I/O interface controller;characterizes a predicted load on the I/O interface based on analysis of the read/write requests in the I/O queue as well as on an existing clock frequency of the I/O interface; and a frequency governor running on the processor that: performs a comparison of the predicted load to one or more thresholds; andcommands the clock control block to decrease the clock signal whenever the predicted load indicates that decreasing the clock signal will not noticeably degrade a user experience.
地址 San Diego CA US