III-V layers for N-type and P-type MOS source-drain contacts

摘要

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

主权项

1. A semiconductor integrated circuit, comprising:
a substrate having a number of channel regions; a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region; p-type source/drain regions comprising silicon in the substrate and adjacent to a corresponding channel region; n-type source/drain regions comprising silicon in the substrate and adjacent to a corresponding channel region; a doped III-V semiconductor material layer on at least a portion of the p-type source/drain regions and a portion of the n-type source/drain regions; and a metal contact on the III-V semiconductor material layer.