Reducing wafer distortion through a high CTE layer

摘要

Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

主权项

1. A method at fabricating a semiconductor device, comprising:
providing a silicon substrate having opposite first and second sides, at least one of the first and second sides including a silicon (111) surface; forming a first high coefficient-of-thermal-expansion (CTE) layer on the first side at the silicon substrate, the first high CTE layer having a CTE greater than a CTE of silicon; forming a buffer layer over the second side of the silicon substrate, the buffer layer having a CTE greater than the CTE of silicon; forming a second high CTE layer over the buffer layer on the second side of the silicon substrate, the second high CTE layer having a CTE greater than the CTE of silicon, wherein the CTE of the second high CTE layer is the same as the CTE of the first high CTE layer, removing the second high CTE layer; and after removing the second high CTE layer, forming a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer.