Method of manufacturing an array substrate

摘要

The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer.

主权项

1. A method of manufacturing an array substrate, comprising:
a first patterning process of forming a first metal layer comprising a gate line and a gate electrode of a thin film transistor (TFT) on a substrate; a second patterning process of forming a first insulating layer to cover the first metal layer and the substrate and sequentially forming a semiconductor layer, an ohmic contact layer, a second metal layer that comprises a data line and a source electrode and a drain electrode of the TFT, and an etch-blocking pattern on the first insulating layer, wherein a lamination of the semiconductor layer and the ohmic contact layer constitutes an active layer of the TFT, and the data line is connected to the source electrode; and a third patterning process of forming a second insulating layer to cover the semiconductor layer, the ohmic contact layer, and the second metal layer, and forming, through a lifting-off process, a pixel electrode connected to the drain electrode of the TFT; wherein the etch-blocking pattern is formed in a peripheral area of the pixel electrode within an overlapping region between the pixel electrode and the first metal layer, and the etch-blocking pattern is interposed between the active layer and the pixel electrode.