发明名称 Mitigating instruction prediction latency with independently filtered presence predictors
摘要 Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.
申请公布号 US9152424(B2) 申请公布日期 2015.10.06
申请号 US201213523784 申请日期 2012.06.14
申请人 International Business Machines Corporation 发明人 Bonanno James J.;Prasky Brian R.;Saporito Anthony;Shum Chung-Lung K.
分类号 G06F9/38 主分类号 G06F9/38
代理机构 Cantor Colburn LLP 代理人 Cantor Colburn LLP ;McNamara Margaret
主权项 1. A computer system for mitigating instruction prediction latency, the system comprising: a processor, the processor including a processor pipeline having an instruction stream, an instruction cache, a prediction presence predictor and a branch target buffer (BTB); wherein the prediction presence predictor further comprises: a plurality of presence predictors configured to each receive an instruction address in parallel and to each generate an unfiltered indication of an associated prediction;a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors, wherein each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to; anda stall determination logic coupled to the plurality of dynamic filters, wherein the stall determination logic is configured to generate a combined indication of the associated prediction based upon one or more filtered indications received from the plurality of dynamic filters; the system configured to perform a method comprising: receiving the instruction address in the instruction cache for fetching instructions in the processor pipeline; receiving the instruction address in the prediction presence predictor coupled to the processor pipeline; based on receipt of the combined indication from the prediction presence predictor, holding instructions extracted from the instructions being fetched when they are determined to be BTB predictable by opcode, but such a prediction is not yet available; and based on the receipt of a branch prediction from a branch target buffer, releasing said held instructions to the processor pipeline for execution.
地址 Armonk NY US