Dynamic offset injection for CMOS ADC front-end linearization

摘要

Disclosed are systems employing a digital background calibration technique for linearizing the front-end circuits of IF-sampling ADCs. The disclosed systems and methods employ a power series model to eliminate the static non-linearity with split-ADC architecture and LMS algorithm for background learning. The present disclosure utilizes a technique for applying two different offset signals to the input of two conversion paths in the split-ADC architecture. When the system nonlinearity is successfully calibrated, the output difference between the two conversion paths results in a fixed offset that is identical to the offset injected at the input. The disclosed digital background calibration technique can linearize the front-end circuits of high-speed ADCs and significantly reduce power consumption.

主权项

1. A method for calibrating split analog-to-digital (ADC) architecture, comprising:
receiving, along a first signal path comprising a first input buffer associated with a first ADC of said split ADC, an input signal; receiving, along a second signal path comprising a second input buffer associated with a second ADC of said split ADC, said input signal, said input signal split between said first signal path and said second signal path; applying an offset to the first signal path; determining, via each split ADC, conversion results for the first signal path and the second signal path, said conversion result for the first signal path is based upon said applied offset; and determining a difference between each conversion result,
wherein if said difference corresponds to a non-constant value, calibrating the split ADC via application of a learning algorithm, andwherein if said difference corresponds to a constant value, identifying the split ADC as a linear system.