Thermal enhanced high density flip chip package

摘要

Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

主权项

1. An integrated circuit (IC) device comprising:
an IC die; a routing layer coupled to a surface of the IC die, wherein the routing layer includes:
a plurality of metallic traces including a first metallic trace, anda molding portion surrounding the plurality of metallic traces, wherein a thickness of the first metallic trace is substantially equal to a thickness of the molding portion, wherein a side portion of the molding portion is coupled to a side portion of the first metallic trace, wherein an entire area of a top surface of the first metallic trace is coplanar with a top surface of the molding portion, and wherein an entire area of a bottom surface of the first metallic trace is coplanar with a bottom surface of the molding portion; and a plurality of substrate connection elements coupled to the routing layer.