Page buffer circuit

摘要

A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

主权项

1. An apparatus comprising:
a page buffer circuit including:
a sense node coupled to a bit line of a memory array;a latch; anda plurality of transistors connected in series between the sense node and the latch; including:
a first transistor having a control terminal coupled to the latch, a first current carrying terminal coupled to the latch, and a second current carrying terminal;a second transistor having a control terminal, a first current carrying terminal coupled to the sense node, and a second current carrying terminal coupled to the second current carrying terminal of the first transistor.