| 主权项 |
1. A flash memory apparatus, comprising:
a plurality of memory cell regions, wherein each of the memory cell regions comprises:
a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point;a programming control voltage generator, coupled to the memory cells, wherein the programming control voltage generator comprises:
a pre-charge voltage transmitter, coupled to all the control end points of the memory cells, providing a pre-charge voltage to the control end point of the memory cells according to a pre-charge enable signal during a first period of time; anda pumping capacitor, coupled between the control end point of the memory cells and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the memory cells; andan erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises:
an erasing pre-charge voltage transmitter, coupled to all the erase end points of the memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; andan erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing. |
