Apparatus for reducing write minimum supply voltage for memory

摘要

Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

主权项

1. An apparatus comprising:
a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to a power supply; a first access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a first bit-line which is operable to be pre-discharged to a logical low level prior to write operation; and a second access device having a gate terminal coupled to the word-line, a first terminal coupled to the memory element, and a second terminal coupled to a second bit-line which is operable to be pre-discharged to a logical low level prior to the write operation, wherein the first and second bit-lines are differential bit-lines, and wherein both the first and second bit-lines are operable to be pre-discharged to a logical low level prior to the write operation such that the power supply on the first supply node exhibits self-induced reduction.