发明名称 GATE BIAS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a gate bias circuit capable of suppressing increases in a gate voltage and a drain current caused by a gate current flowing from a source of an FET amplifier to a gate when a large signal whose power is large is inputted.SOLUTION: The gate bias circuit includes: a main line 101 for connecting between an input terminal 1 and an output terminal 2 connected to a gate of an amplifier; a bias line 6 of which one end is connected to the main line between the input terminal and the output terminal and the other end is connected to a gate bias terminal 3; an open stub 5 connected to the bias line; and a radio wave absorber 7 attached in contact with the bias line so as to surround the bias line between an intersection of the main line and a bias line and the open stub.
申请公布号 JP2015177291(A) 申请公布日期 2015.10.05
申请号 JP20140051438 申请日期 2014.03.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 MIZUTANI TOMOHIRO
分类号 H03F3/60;H03F3/193 主分类号 H03F3/60
代理机构 代理人
主权项
地址