| 摘要 |
Provided is a data converter which is provided with a clock signal input unit which inputs a clock signal an input unit which inputs an input signal a sampling unit which in response to the clock signal inputted to the clock signal input unit performs sampling of the input signal inputted to the input unit and a signal processing unit which performs signal processing in accordance with the sampling period and outputs an output signal wherein if the period of the clock signal inputted to the clock signal input unit becomes longer the output signals outputted by the signal processing unit are reduced. |
