| 发明名称 |
POWER GATING CIRCUIT AND INTEGRATED CIRCUIT |
| 摘要 |
A power gating circuit in an integrated circuit, including a circuit block coupled to a virtual power supply line, includes a first transistor and a buffer. The first transistor is coupled between a first power supply line and the virtual power supply line, and has a body coupled to the first power supply line. The buffer buffers a control signal to apply the buffered control signal to the first transistor, and includes a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line. |
| 申请公布号 |
US2015280703(A1) |
申请公布日期 |
2015.10.01 |
| 申请号 |
US201514616824 |
申请日期 |
2015.02.09 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JEON JAE-HAN |
| 分类号 |
H03K17/16;G05F1/46;H03K17/687 |
主分类号 |
H03K17/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A power gating circuit in an integrated circuit including a circuit block coupled to a virtual power supply line, the power gating circuit comprising:
a first transistor coupled between a first power supply line and the virtual power supply line, the first transistor having a body coupled to the first power supply line; and a buffer configured to buffer a control signal to apply the buffered control signal to the first transistor, the buffer including a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line. |
| 地址 |
SUWON-SI KR |
