| 发明名称 |
WAFER PACKAGE PROCESS |
| 摘要 |
A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material. |
| 申请公布号 |
US2015279829(A1) |
申请公布日期 |
2015.10.01 |
| 申请号 |
US201414226802 |
申请日期 |
2014.03.26 |
| 申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
Kuo Chien-Li |
| 分类号 |
H01L25/00;H01L23/00;H01L21/78;H01L21/56;H01L21/311;H01L25/065;H01L21/768 |
主分类号 |
H01L25/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A wafer package process, comprising:
providing a wafer with a plurality of first dies; bonding a plurality of second dies on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die; forming a molding material to entirely cover the second dies and the wafer; forming a through via in the molding material; and forming a conductive material filling the through via as well as onto the molding material. |
| 地址 |
Hsin-Chu City TW |
