APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE

摘要

Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

主权项

1. An integrated circuit (IC) package comprising:
a command and address bus; and a plurality of memory chips each coupled to the command and address bus, each of the plurality of memory chips including a respective on-die termination control circuit corresponding to the command and address bus; wherein, of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus; and wherein, of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package.