发明名称 |
METHOD AND APPARATUS FOR PERFORMING A PLURALITY OF MULTIPLICATION OPERATIONS |
摘要 |
An apparatus and method are described for performing a plurality of multiplication operations. For example, one embodiment of a processor comprises an instruction fetch unit to fetch a double-multiplication instruction from a memory subsystem, the double-multiplication instruction having three source operand values; a decode unit to decode the double-multiplication instruction to generate at least one uop; and an execution unit to execute the uop a first time to multiply a first and a second of the three source operand values to generate a first intermediate result and to execute the uop a second time to multiply the intermediate result with a third of the three source operand values to generate a final result. |
申请公布号 |
US2015277904(A1) |
申请公布日期 |
2015.10.01 |
申请号 |
US201414229183 |
申请日期 |
2014.03.28 |
申请人 |
ESPASA ROGER;SOLE GUILLEM;FERNANDEZ MANEL |
发明人 |
ESPASA ROGER;SOLE GUILLEM;FERNANDEZ MANEL |
分类号 |
G06F9/30;G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
an instruction fetch unit to fetch a double-multiplication instruction from a memory subsystem, the double-multiplication instruction having three source operand values; a decode unit to decode the double-multiplication instruction to generate at least one uop; and an execution unit to execute the uop a first time to multiply a first and a second of the three source operand values to generate a first intermediate result and to execute the uop a second time to multiply the intermediate result with a third of the three source operand values to generate a final result. |
地址 |
Barcelona ES |