STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS

摘要

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

主权项

1. A method of forming a semiconductor structure comprising:
providing a semiconductor substrate having an nFET device region and a pFET device region; and providing an EOT scaled nFET in said nFET device region and an EOT scaled pFET in said pFET device region, said EOT scaled nFET including, from bottom to top, an nFET modified interfacial layer including an nFET threshold voltage adjusting element incorporated therein, a first high k gate dielectric portion, a first metallic electrode portion and a first Si-containing electrode portion, and said EOT scaled pFET including, from bottom to top, a pFET modified interfacial layer including a pFET threshold voltage adjusting element incorporated therein, a second high k gate dielectric portion, a second metallic electrode portion and a second Si-containing electrode portion.