Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping

摘要

The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.

主权项

1. A method of aspect ratio trapping (ART) with reduced line-edge-roughness (LER), the method comprising the steps of:
providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer, thereby reducing an LER of the ART lines in the silicon layer as compared to a LER of the ART lines as patterned in the silicon layer, resulting in formation of a smoothened, patterned silicon layer; using the smoothened, patterned silicon layer to pattern one or more ART trenches in the dielectric layer, wherein the substrate is exposed at a bottom of each of the trenches; and epitaxially growing a semiconductor material in the trenches, up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.