LOGIC ANALYZER CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE

摘要

The present disclosure relates to methods and related systems and computer-readable mediums. The methods include receiving a design for a programmable logic device (PLD). The design includes a plurality of nodes. The method also includes modifying, via one or more hardware processors, the design to include a logic analyzer circuit. The logic analyzer circuit includes inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes. In addition, the method includes outputting the design to the PLD to program the PLD. The disclosure also relates a system comprising a user logic circuit, a logic analyzer circuit, and a memory.

主权项

1. A computer-implemented method comprising:
receiving a design for a programmable logic device (PLD), the design including a plurality of nodes; modifying, via one or more hardware processors, the design to include a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes; and outputting the design to the PLD to program the PLD.