| 发明名称 |
CO-DESIGNED DYNAMIC LANGUAGE ACCELERATOR FOR A PROCESSOR |
| 摘要 |
In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed. |
| 申请公布号 |
US2015277866(A1) |
申请公布日期 |
2015.10.01 |
| 申请号 |
US201414225755 |
申请日期 |
2014.03.26 |
| 申请人 |
Wang Cheng;Wu Youfeng;Rong Hongbo;Park Hyunchul |
发明人 |
Wang Cheng;Wu Youfeng;Rong Hongbo;Park Hyunchul |
| 分类号 |
G06F9/45;G06F9/455 |
主分类号 |
G06F9/45 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system comprising:
a processor to execute instructions, the processor including at least one core and a dynamic language accelerator to execute bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator, wherein the processor is to block execution of native code while the dynamic language accelerator executes the bytecode; and a system memory coupled to the processor. |
| 地址 |
San Ramon CA US |
