发明名称 |
METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES |
摘要 |
3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material. |
申请公布号 |
WO2015148055(A1) |
申请公布日期 |
2015.10.01 |
申请号 |
WO2015US18138 |
申请日期 |
2015.02.27 |
申请人 |
INTEL CORPORATION |
发明人 |
FAN, DARWIN;KOKA, SATEESH;HALLER, GORDON;HOPKINS, JOHN;SURTHI, SHYAM;KHANDEKAR, ANISH |
分类号 |
H01L27/115;H01L21/8247 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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