DISPLAY DEVICE

摘要

A liquid crystal panel 11 includes a display area TFT 17, a non-display area TFT 29, and a first interlayer insulator 39. The display area TFT 17 is disposed in a display area AA of an array board 11b. The non-display area TFT 29 is disposed in a non-display area NAA. The non-display area TFT 29 includes a second gate electrode 29a, a second channel 29d, a second source electrode 29b, and a second drain electrode 29c. The second channel 29d is formed from an oxide semiconductor film 36. The second source electrode 29b is connected to the second channel 29d. The second drain electrode 29c is connected to the second channel 29d. The first interlayer insulator 39 is layered at least on the second source electrode 29b and the second drain electrode 29c. The first interlayer insulator 39 has a multilayer structure including a lower first interlayer insulator 39a and an upper first interlayer insulator 39b. The lower first interlayer insulator 39a is disposed in a lower layer and contains at least silicon and oxygen. The upper first interlayer insulator 39b is disposed in an upper layer and contains at least silicon and nitrogen. The upper first interlayer insulator 39b has a thickness in a range from 35 nm to 75 nm.

主权项

1. A display device comprising:
a substrate including a display area and a non-display area, the display area being configured to display images and located medially, the non-display area being located closer to peripheral edges of the substrate so as to surround the display area; a display area transistor disposed in the display area; s non-display area transistor disposed in the non-display area; a gate electrode included in the non-display area transistor; an oxide semiconductor film included in the non-display area transistor, at least a portion of the oxide semiconductor film overlapping the gate electrode in a plan view; a source electrode included in the non-display area transistor, at least a portion of the source electrode being layered on the oxide semiconductor film in a plan view and connected to the oxide semiconductor film; a drain electrode included in the non-display area transistor, at least a portion of the drain electrode being layered on the oxide semiconductor film and connected to the oxide semiconductor film with a gap between the source electrode and the drain electrode; and an insulator layered on the source electrode and the drain electrode, the insulator having a multilayer structure including a lower insulator and an upper insulator, the lower insulator disposed in a lower layer and containing at least silicon and oxygen, the upper insulator disposed in an upper layer and containing at least silicon and nitrogen, the upper insulator having a thickness in a range from 35 nm to 75 nm.